Staircase structures for three-dimensional memory device double-sided routing

ABSTRACT

Embodiments of staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed above the substrate and including conductor/dielectric layer pairs stacked alternatingly, and an array of memory strings each extending vertically through an inner region of the memory stack. An outer region of the memory stack includes a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure. First edges of the conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings. Second edges of the conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.

CROSS REFERENCE TO RELATED APPLICATION

This application is continuation of International Application No.PCT/CN2018/093257, filed on Jun. 28, 2018, entitled “STAIRCASESTRUCTURES FOR THREE-DIMENSIONAL MEMORY DEVICE DOUBLE-SIDED ROUTING,”which is hereby incorporated by reference in its entirety. Thisapplication is also related to U.S. application Ser. No. 16/138,992,filed on even date, entitled “METHOD OF FORMING STAIRCASE STRUCTURES FORTHREE-DIMENSIONAL MEMORY DEVICE DOUBLE-SIDED ROUTING,” which is herebyincorporated by reference in its entirety.

BACKGROUND

Embodiments of the present disclosure relate to three-dimensional (3D)memory devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving processtechnology, circuit design, programming algorithm, and fabricationprocess. However, as feature sizes of the memory cells approach a lowerlimit, planar process and fabrication techniques become challenging andcostly. As a result, memory density for planar memory cells approachesan upper limit.

A 3D memory architecture can address the density limitation in planarmemory cells. The 3D memory architecture includes a memory array andperipheral devices for controlling signals to and from the memory array.

SUMMARY

Embodiments of staircase structures for 3D memory device double-sidedrouting are disclosed herein.

In one example, a 3D memory device includes a substrate, a memory stackdisposed above the substrate and including a plurality ofconductor/dielectric layer pairs stacked alternatingly, and an array ofmemory strings each extending vertically through an inner region of thememory stack. An outer region of the memory stack includes a firststaircase structure disposed on the substrate and a second staircasestructure disposed above the first staircase structure. First edges ofthe plurality of conductor/dielectric layer pairs in the first staircasestructure along a vertical direction away from the substrate arestaggered laterally away from the array of memory strings. Second edgesof the plurality of conductor/dielectric layer pairs in the secondstaircase structure along the vertical direction away from the substrateare staggered laterally toward the array of memory strings.

In another example, a 3D memory device includes a substrate, a memorystack disposed above the substrate and including a plurality ofconductor/dielectric layer pairs stacked alternatingly, and an array ofmemory strings each extending vertically through an inner region of thememory stack. An outer region of the memory stack includes a firststaircase structure disposed on the substrate and a second staircasestructure disposed on the substrate. First edges of the plurality ofconductor/dielectric layer pairs in the first staircase structure alonga vertical direction away from the substrate are staggered laterallyaway from the array of memory strings. Second edges of the plurality ofconductor/dielectric layer pairs in the second staircase structure alongthe vertical direction away from the substrate are staggered laterallyaway from the array of memory strings.

In still another example, a 3D memory device includes a substrate, amemory stack disposed above the substrate, and an array of memorystrings each extending vertically through the memory stack. The memorystack includes a plurality of conductor/dielectric layer pairs stackedalternatingly. A length of each of the conductor/dielectric layer pairsdecreases from a middle conductor/dielectric layer pair toward a topconductor/dielectric layer and a bottom conductor/dielectric layer pair,respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a partof the specification, illustrate embodiments of the present disclosureand, together with the description, further serve to explain theprinciples of the present disclosure and to enable a person skilled inthe pertinent art to make and use the present disclosure.

FIG. 1 illustrates a cross-section of an exemplary 3D memory devicehaving staircase structures for double-sided routing, according to someembodiments.

FIG. 2 illustrates a plan view of an exemplary memory stack in a 3Dmemory device, according to some embodiments.

FIG. 3A illustrates a cross-section of an exemplary 3D memory devicehaving staircase structures for double-sided routing to interconnectlayers, according to some embodiments.

FIG. 3B illustrates a cross-section of another exemplary 3D memorydevice having staircase structures for double-sided routing tointerconnect layers, according to some embodiments.

FIGS. 4A-4I illustrate a fabrication process for forming an exemplary 3Dmemory device having staircase structures for double-sided routing,according to some embodiments.

FIG. 5 is a flowchart of a method for forming an exemplary 3D memorydevice having staircase structures for double-sided routing, accordingto some embodiments.

Embodiments of the present disclosure will be described with referenceto the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, itshould be understood that this is done for illustrative purposes only. Aperson skilled in the pertinent art will recognize that otherconfigurations and arrangements can be used without departing from thespirit and scope of the present disclosure. It will be apparent to aperson skilled in the pertinent art that the present disclosure can alsobe employed in a variety of other applications.

It is noted that references in the specification to “one embodiment,”“an embodiment,” “an example embodiment,” “some embodiments,” etc.,indicate that the embodiment described may include a particular feature,structure, or characteristic, but every embodiment may not necessarilyinclude the particular feature, structure, or characteristic. Moreover,such phrases do not necessarily refer to the same embodiment. Further,when a particular feature, structure or characteristic is described inconnection with an embodiment, it would be within the knowledge of aperson skilled in the pertinent art to effect such feature, structure orcharacteristic in connection with other embodiments whether or notexplicitly described.

In general, terminology may be understood at least in part from usage incontext. For example, the term “one or more” as used herein, dependingat least in part upon context, may be used to describe any feature,structure, or characteristic in a singular sense or may be used todescribe combinations of features, structures or characteristics in aplural sense. Similarly, terms, such as “a,” “an,” or “the,” again, maybe understood to convey a singular usage or to convey a plural usage,depending at least in part upon context. In addition, the term “basedon” may be understood as not necessarily intended to convey an exclusiveset of factors and may, instead, allow for existence of additionalfactors not necessarily expressly described, again, depending at leastin part on context.

It should be readily understood that the meaning of “on,” “above,” and“over” in the present disclosure should be interpreted in the broadestmanner such that “on” not only means “directly on” something but alsoincludes the meaning of “on” something with an intermediate feature or alayer therebetween, and that “above” or “over” not only means themeaning of “above” or “over” something but can also include the meaningit is “above” or “over” something with no intermediate feature or layertherebetween (i.e., directly on something).

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper,” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto whichsubsequent material layers are added. The substrate itself can bepatterned. Materials added on top of the substrate can be patterned orcan remain unpatterned. Furthermore, the substrate can include a widearray of semiconductor materials, such as silicon, germanium, galliumarsenide, indium phosphide, etc. Alternatively, the substrate can bemade from an electrically non-conductive material, such as a glass, aplastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion includinga region with a thickness. A layer can extend over the entirety of anunderlying or overlying structure or may have an extent less than theextent of an underlying or overlying structure. Further, a layer can bea region of a homogeneous or inhomogeneous continuous structure that hasa thickness less than the thickness of the continuous structure. Forexample, a layer can be located between any pair of horizontal planesbetween, or at, a top surface and a bottom surface of the continuousstructure. A layer can extend laterally, vertically, and/or along atapered surface. A substrate can be a layer, can include one or morelayers therein, and/or can have one or more layer thereupon, thereabove,and/or therebelow. A layer can include multiple layers. For example, aninterconnect layer can include one or more conductor and contact layers(in which interconnect lines and/or via contacts are formed) and one ormore dielectric layers.

As used herein, the term “nominal/nominally” refers to a desired, ortarget, value of a characteristic or parameter for a component or aprocess operation, set during the design phase of a product or aprocess, together with a range of values above and/or below the desiredvalue. The range of values can be due to slight variations inmanufacturing processes or tolerances. As used herein, the term “about”indicates the value of a given quantity that can vary based on aparticular technology node associated with the subject semiconductordevice. Based on the particular technology node, the term “about” canindicate a value of a given quantity that varies within, for example,10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

As used herein, the term “3D memory device” refers to a semiconductordevice with vertically oriented strings of memory cell transistors(referred to herein as “memory strings,” such as NAND memory strings) ona laterally-oriented substrate so that the memory strings extend in thevertical direction with respect to the substrate. As used herein, theterm “vertical/vertically” means nominally perpendicular to the lateralsurface of a substrate.

In some 3D memory devices, memory cells for storing data are verticallystacked through a stacked storage structure (e.g., a memory stack). 3Dmemory devices usually include staircase structures formed on one ormore sides of the stacked storage structure for purposes such as wordline fan-out. As the demand for higher storage capacity continues toincrease, the number of vertical levels of the stacked storage structurealso increases. The conventional staircase structures allow word linefan-out toward only one side of the substrate. That is, all the wordline contacts have to land on the conventional staircases along the samevertical direction, which constrains interconnect routing and results inhigher interconnect density and smaller process window.

Various embodiments in accordance with the present disclosure provide a3D memory device having staircase structures for double-sided routing.The staircase structures disclosed herein allow interconnect routing(e.g., word line fan-out) toward both sides of the device substrate,thereby increasing routing flexibility, reducing interconnect density,and enlarging process window. In some embodiments, double-sided routingof a 3D memory device may also eliminate the need of certaininterconnect structures with high aspect ratios, such as through arraycontacts (TACs), in the 3D memory device for back-end-of-line (BEOL)interconnects, which can further improve device yield.

FIG. 1 illustrates a cross-section of an exemplary 3D memory device 100having staircase structures for double-sided routing, according to someembodiments of the present disclosure. 3D memory device 100 can includea substrate 102, which can include silicon (e.g., single crystallinesilicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium(Ge), silicon on insulator (SOI), or any other suitable materials. Insome embodiments, substrate 102 is a thinned substrate (e.g., asemiconductor layer), which was thinned from a normal thickness bygrinding, wet/dry etching, chemical mechanical polishing (CMP), or anycombination thereof.

3D memory device 100 can include a memory stack 104 above substrate 102.Memory stack 104 can be a stacked storage structure through which memorystrings (e.g., NAND memory strings 106) are formed. In some embodiments,memory stack 104 includes a plurality of conductor/dielectric layerpairs 108 stacked vertically above substrate 102. Eachconductor/dielectric layer pair 108 can include a conductor layer 110and a dielectric layer 112. That is, memory stack 104 can includeinterleaved conductor layers 110 and dielectric layers 112 stackedvertically. As shown in FIG. 1, each NAND memory string 106 extendsvertically through conductor/dielectric layer pairs 108 in memory stack104. In some embodiments, 3D memory device 100 is a NAND Flash memorydevice in which memory cells are provided at intersections of NANDmemory strings 106 and conductor layers 110 (functioning as word lines)of 3D memory device 100. The number of conductor/dielectric layer pairs108 in memory stack 104 (e.g., 32, 64, 96, or 128) can set the number ofmemory cells in 3D memory device 100.

Conductor layers 110 can each have the same thickness or have differentthicknesses. Similarly, dielectric layers 112 can each have the samethickness or have different thicknesses. Conductor layers 110 caninclude conductive materials including, but not limited to, tungsten(W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon(polysilicon), doped silicon, silicides, or any combination thereof.Dielectric layers 112 can include dielectric materials including, butnot limited to, silicon oxide, silicon nitride, silicon oxynitride, orany combination thereof. In some embodiments, conductor layers 110include metal layers, such as W, and dielectric layers 112 includesilicon oxide. It is understood that a silicon oxide film 114, such asan in-situ steam generation (ISSG) silicon oxide, is formed betweensubstrate 102 (e.g., a silicon substrate) and memory stack 104,according to some embodiments.

It is noted that x and y axes are added to FIG. 1 to further illustratethe spatial relationship of the components in 3D memory device 100.Substrate 102 includes two lateral surfaces (e.g., a top surface and abottom surface) extending laterally in the x-direction (the lateraldirection or width direction). As used herein, whether one component(e.g., a layer or a device) is “on,” “above,” or “below” anothercomponent (e.g., a layer or a device) of a semiconductor device (e.g.,3D memory device 100) is determined relative to the substrate of thesemiconductor device (e.g., substrate 102) in the y-direction (thevertical direction or thickness direction) when the substrate ispositioned in the lowest plane of the semiconductor device in they-direction. The same notion for describing spatial relationship isapplied throughout the present disclosure.

In some embodiments, 3D memory device 100 is part of a monolithic 3Dmemory device, in which the components of the monolithic 3D memorydevice (e.g., memory cells and peripheral devices) are formed on asingle substrate (e.g., substrate 102). Peripheral devices (not shown),such as any suitable digital, analog, and/or mixed-signal peripheralcircuits used for facilitating the operation of 3D memory device 100,can be formed above memory stack 104. In some embodiments, 3D memorydevice 100 is part of a non-monolithic 3D memory device, in which thecomponents are formed separately on different substrates and then bondedin a face-to-face manner, a face-to-back manner, or a back-to-backmanner Peripheral devices (not shown) can be formed on a separatesubstrate different from substrate 102. As part of a bondednon-monolithic 3D memory device, substrate 102 can be a thinnedsubstrate (e.g., a semiconductor layer, which is not the substrate ofthe bonded non-monolithic 3D memory device), and the BEOL interconnectsof the non-monolithic 3D memory device can be formed on the backside ofthinned substrate 102.

Nevertheless, 3D memory device 100 can be part of a monolithic ornon-monolithic 3D memory device regardless of whether 3D memory device100 is above or below the peripheral devices (not shown). For ease ofreference, FIG. 1 depicts a state of 3D memory device 100 in whichsubstrate 102 is positioned below memory stack 104 in the y-direction,regardless of whether substrate 102 is a thinned substrate on which theBEOL interconnects of 3D memory device 100 can be formed.

As shown in FIG. 1, memory stack 104 can include an inner region 116(also known as a “core array region”) and an outer region 118 (alsoknown as a “staircase region”). In some embodiments, inner region 116 isthe center region of memory stack 104 where an array of NAND memorystrings 106 are formed through conductor/dielectric layer pairs 108, andouter region 118 is the remaining region of memory stack 104 surroundinginner region 116 (including the sides and edges) without NAND memorystrings 106. As shown in the plan view of FIG. 2, memory stack 104 canhave a rectangle (or square) shape with inner region 116 in the centerand outer region 118 (including the four sides and edges) surroundinginner region 116.

As shown in FIG. 1, each NAND memory string 106 can extend verticallythrough inner region 116 of memory stack 104. Each NAND memory string106 can include a channel hole filled with semiconductor materials(e.g., forming a semiconductor channel 120) and dielectric materials(e.g., forming a memory film 122). In some embodiments, semiconductorchannel 120 includes silicon, such as amorphous silicon, polysilicon, orsingle crystalline silicon. In some embodiments, memory film 122 is acomposite layer including a tunneling layer, a storage layer (also knownas a “charge trap/storage layer”), and a blocking layer. Each NANDmemory string 106 can have a cylinder shape (e.g., a pillar shape).Semiconductor channel 120, the tunneling layer, the storage layer, andthe blocking layer are arranged along a direction from the center towardthe outer surface of the pillar in this order, according to someembodiments. The tunneling layer can include silicon oxide, siliconoxynitride, or any combination thereof. The storage layer can includesilicon nitride, silicon oxynitride, silicon, or any combinationthereof. The blocking layer can include silicon oxide, siliconoxynitride, high dielectric constant (high-k) dielectrics, or anycombination thereof.

In some embodiments, NAND memory strings 106 include a plurality ofcontrol gates (each being part of a word line/conductor layer 110) forNAND memory strings 106. Conductor layer 110 in eachconductor/dielectric layer pair 108 can function as a control gate formemory cells of NAND memory string 106. Conductor layer 110 can includemultiple control gates for multiple NAND memory strings 106 and canextend laterally as a word line ending at the edge of memory stack 104.It is understood that although not shown in FIG. 1, additionalcomponents of 3D memory device 100 can be formed as part of NAND memorystrings 106 and/or memory stack 104 including, but not limited to, arraycommon sources, drains, source select gates, drain select gates, andgate line slits/source contacts.

As shown in FIG. 1, at least on two sides in the lateral direction,outer region 118 of memory stack 104 can include multiple staircasestructures 124. In some embodiments, memory stack 104 includes a firststaircase structure 124A on substrate 102 and a second staircasestructure 124B above first staircase structure 124A on one side and athird staircase structure 124C on substrate 102 and a fourth staircasestructure 124D above third staircase structure 124C on another side.That is, memory stack 104 can include a lower deck 126 and an upper deck128, with first and third staircase structures 124A and 124C in lowerdeck 126 and second and fourth staircase structures 124B and 124D inupper deck 128.

In each staircase structure 124A or 124C in lower deck 126,corresponding edges of conductor/dielectric layer pairs 108 along thevertical direction away from substrate 102 (the positive y-direction)can be staggered laterally away from array of NAND memory strings 106 ofmemory stack 104. In other words, the edges of memory stack 104 instaircase structures 124A and 124C in lower deck 126 can be tilted awayfrom inner region 116 as moving away from substrate 102 (from bottom totop). In some embodiments, the length of conductor/dielectric layerpairs 108 in lower deck 126 of memory stack 104 decreases from the topto the bottom.

On the other hand, in each staircase structure 124B or 124D in upperdeck 128, corresponding edges of conductor/dielectric layer pairs 108along the vertical direction away from substrate 102 (the positivey-direction) can be staggered laterally toward array of NAND memorystrings 106 of memory stack 104. In other words, the edges of memorystack 104 in staircase structures 124B and 124D in upper deck 128 can betilted toward inner region 116 as moving away from substrate 102 (frombottom to top). In some embodiments, the length of conductor/dielectriclayer pairs 108 in upper deck 128 of memory stack 104 increases from thebottom to the top.

Consequently, as shown in FIG. 1, memory stack 104 can have asubstantially hexagon shape in the side view (disregarding the“sawtooth” on the sides). The length of each conductor/dielectric layerpair 108 can decrease from the middle toward the top and the bottom,respectively. For example, the length of each conductor/dielectric layerpair 108 decreases from a middle conductor/dielectric layer pair towarda top conductor/dielectric layer pair and also decreases from a middleconductor/dielectric layer pair toward a bottom conductor/dielectriclayer pair, as shown in FIG. 1. One or more conductor/dielectric layerpairs in the middle of memory stack 104 can have the largest length. Insome embodiments, conductor/dielectric layer pairs 108 in each of lowerand upper decks 126 and 128 are vertically symmetric. For example, thenumbers of conductor/dielectric layer pairs 108 in first and thirdstaircase structures 124A and 124C in lower deck 126 are the same, andthe numbers of conductor/dielectric layers pairs 108 in second andfourth staircase structures 124B and 124D in upper deck 128 are thesame. In some embodiments, conductor/dielectric layer pairs 108 in lowerand upper decks 126 and 128 are laterally symmetric. For example, thenumbers of conductor/dielectric layer pairs 108 in first and secondstaircase structures 124A and 124B are the same, and the numbers ofconductor/dielectric layer pairs 108 in third and fourth staircasestructures 124C and 124D are the same.

Each “level” of staircase structure 124 can include one or moreconductor/dielectric layer pairs 108, each including a pair of conductorlayer 110 and dielectric layer 112. As shown in FIG. 1, each level ofstaircase structure 124 includes one conductor/dielectric layer pair108, according to some embodiments. Each adjacent conductor/dielectriclayer pairs 108 can have different lengths, and their edges arestaggered laterally. For example, the edges of each adjacentconductor/dielectric layer pairs 108 in first or third staircasestructure 124A or 124C in lower deck 126 from bottom to top arestaggered laterally away from array of NAND memory strings 106, and theedges of each adjacent conductor/dielectric layer pairs 108 in second orfourth staircase structure 124B or 124D in upper deck 128 from bottom totop are staggered laterally toward NAND memory strings 106. It isunderstood that in some embodiments, each level of staircase structure124 can include multiple conductor/dielectric layer pairs 108 eachhaving nominally the same length.

In some embodiments, the top layer in each level of staircase structure124 (e.g., each conductor/dielectric layer pair 108 in FIG. 1) isconductor layer 110 for interconnection in the vertical directions. Insome embodiments, each two adjacent levels of staircase structure 124are offset by a nominally same distance in the vertical direction and anominally same distance in the lateral direction. Each offset thus canform a “landing area” for interconnection with the word lines of 3Dmemory device 100 in the vertical direction. As shown in FIG. 1, theoffset of the edges of each adjacent conductor/dielectric layer pairs108 in each staircase structure 124A, 124B, 124C, or 124D is nominallythe same, according to some embodiments.

Referring to the plan view of FIG. 2, memory stack 104 has staircasestructures on four sides of outer region 118, according to someembodiments. FIG. 1 illustrates the cross-section of memory stack 104along the A-A′ direction with four staircase structures 124A-124D on twoopposite sides. In some embodiments, outer region 118 of memory stack104 further includes four staircase structures along the B-B′ directionon another two opposite sides, which have the similar design andconfiguration as staircase structures 124A-124D in FIG. 1. For example,the cross-section of memory stack 104 along the B-B′ direction can alsohave a substantially hexagon shape in the side view. The details of thefour staircase structures along the B-B′ direction will not be repeated.A staircase structure can be either a functional staircase structureused for landing interconnects (e.g., via contacts) and/or dummy channelholes or a dummy staircase structure used for balancing load in etch/CMPprocesses during fabrication. In some embodiments, the staircasestructures along the A-A′ direction (e.g., staircase structures124A-124D in FIG. 1) are functional staircase structures, while thestaircase structures along the B-B's direction are dummy staircasestructures.

Referring back to FIG. 1, 3D memory device 100 can include a pluralityof local interconnects in contact with the various memory stackcomponents disclosed herein, such as NAND memory strings 106 and wordlines 110 in staircase structures 124. The interconnects are referred toherein as “local interconnects” as they are in contact with thecomponents in memory stack 104 directly for fan-out. As used herein, theterm “interconnects” can broadly include any suitable types ofinterconnects, including vertical interconnect access (e.g., via)contacts and lateral interconnect lines. As shown in FIG. 1, localinterconnects can include word line via contacts 130 and NAND memorystring via contacts 132. Each local interconnect can include an opening(e.g., a via hole or a trench) filled with conductive materialsincluding, but not limited to, W, Co, Cu, Al, silicides, or anycombination thereof.

The hexagon-shaped memory stack 104 shown in FIG. 1 can allowdouble-sided interconnect routing for 3D memory device 100, such asdouble-sided word line fan-out using staircase structures 124 in bothlower and upper decks 126 and 128. Interconnect routing thus can beachieved at opposite sides of substrate 102. In some embodiments, wordline via contacts 130 include a first set of word line via contacts 130Aand a third set of word line via contacts 130C for word line fan-out inlower deck 126 toward substrate 102 (the negative y-direction) andinclude a second set of word line via contacts 130B and a fourth set ofword line via contacts 130D for word line fan-out in upper deck 128 awayfrom substrate 102 (the positive y-direction). For first and third setsof word line via contacts 130A and 130C, each of them can be in contactwith conductor layer 110 (word line) in one of conductor/dielectriclayer pairs 108 in respective staircase structure 124A or 124C in lowerdeck 126. Similarly, for second and fourth sets of word line viacontacts 130B and 130D, each of them can be in contact with conductorlayer 110 (word line) in one of conductor/dielectric layer pairs 108 inrespective staircase structure 124B or 124D in upper deck 128.

As each word line 110 can be fanned-out by one of the staircasestructures on either side of the same deck, for each staircase structure124, not all of the landing areas need to be used for contacting wordline via contact 130. In some embodiments, each staircase structure 124is used to fan-out one half of word lines 110 in the corresponding deck.For example, word lines 110 can be alternatingly fanned-out by twostaircase structures 124 in the same deck.

The hexagon-shaped memory stack 104 shown in FIG. 1 can allowdouble-sided interconnect routing for 3D memory device 100, which inturn can allow interconnect layers (e.g., BEOL interconnects) at eitherone or both sides of substrate 102 to be electrically connected to thecomponents (e.g., word lines 110) in memory stack 104 by the localinterconnects (e.g., word line via contacts 130). For example, FIGS.3A-3B illustrate cross-sections of 3D memory device 100 having staircasestructures 124 for double-sided routing to interconnect layers,according to various embodiments.

As shown in FIG. 3A, 3D memory device 100 can include a front-sideinterconnect layer 302 above memory stack 104 and at the front side ofsubstrate 102 where memory stack 104 is formed. Front-side interconnectlayer 302 can include interconnect lines 304 and via contacts 306 andone or more interlayer dielectric (ILD) layers (also known as“intermetal dielectric (IMD) layers”) in which interconnect lines 304and via contacts 306 can form. The interconnects (e.g., interconnectlines 304 and via contacts 306) and the ILD layers can be collectivelyreferred to herein as an “interconnect layer” (e.g., front-sideinterconnect layer 302). Interconnect lines 304 and via contacts 306 caninclude conductive materials including, but not limited to, W, Co, Cu,Al, silicides, or any combination thereof. The ILD layers in front-sideinterconnect layer 302 can include dielectric materials including, butnot limited to, silicon oxide, silicon nitride, silicon oxynitride, lowdielectric constant (low-k) dielectrics, or any combination thereof.

In some embodiments, one end (e.g., the lower end) of each word line viacontact 130B is in contact with a word line in staircase structure 124B,and another end (e.g., the upper end) of each word line via contact 130Bis in contact with the interconnects in front-side interconnect layer302. That is, front-side interconnect layer 302 can be electricallyconnected to the word lines in the upper deck of memory stack 104. Asused herein, the “upper end” of a component (e.g., word line via contact130) is the end farther away from substrate 102 in the y-direction, andthe “lower end” of the component is the end closer to substrate 102 inthe y-direction.

As shown in FIG. 3A, 3D memory device 100 can also include a back-sideinterconnect layer 308 below memory stack 104 and at the back side ofsubstrate 102. That is, back-side interconnect layer 308 and memorystack 104 can be formed at opposite sides of substrate 102. Back-sideinterconnect layer 308 can include interconnect lines 310 and viacontacts 312 and one or more ILD layers in which interconnect lines 310and via contacts 312 can form. The interconnects (e.g., interconnectlines 310 and via contacts 312) and the ILD layers can be collectivelyreferred to herein as an “interconnect layer” (e.g., back-sideinterconnect layer 308). Interconnect lines 310 and via contacts 312 caninclude conductive materials including, but not limited to, W, Co, Cu,Al, silicides, or any combination thereof. The ILD layers in back-sideinterconnect layer 308 can include dielectric materials including, butnot limited to, silicon oxide, silicon nitride, silicon oxynitride, lowk dielectrics, or any combination thereof.

In some embodiments, one end (e.g., the upper end) of each word line viacontact 130D is in contact with a word line in staircase structure 124D,and another end (e.g., the lower end) of each word line via contact 130Dis in contact with a via contact 314 extending through substrate 102(e.g., a through silicon via (TSV)). Via contacts 314 can be in contactwith the interconnects in back-side interconnect layer 308. As a result,back-side interconnect layer 308 can be electrically connected to theword lines in the lower deck of memory stack 104 by word line viacontacts 130D and via contacts 314 through substrate 102. It isunderstood that in some embodiments, substrate 102 is a thinnedsubstrate for ease of forming via contacts 314 and back-sideinterconnect layer 308.

In some embodiments, not all staircase structures 124A-124D need to beused for word line fan-out. Only one staircase structure 124 in each oflower deck 126 and upper deck 128 is used, according to someembodiments. In one example, FIG. 3A shows that only staircasestructures 124B and 124D in different decks and on different sides ofmemory stack 104 are used for word line fan-out to interconnect layers302 and 308 at different sides of substrate 102. It is understood thatin some embodiments, only staircase structures 124A and 124C indifferent decks and on different sides of memory stack 104 are used forword line fan-out. In another example, FIG. 3B shows that only staircasestructures 124A and 124B in different decks and on the same side ofmemory stack 104 are used for word line fan-out to interconnect layers302 and 308 at different sides of substrate 102. It is understood thatin some embodiments, only staircase structures 124C and 124D indifferent decks and on the same side of memory stack 104 are used forword line fan-out.

FIGS. 4A-4I illustrate a fabrication process for forming an exemplary 3Dmemory device having staircase structures for double-sided routing,according to some embodiments of the present disclosure. FIG. 5 is aflowchart of a method 500 for forming an exemplary 3D memory devicehaving staircase structures for double-sided routing, according to someembodiments. Examples of the 3D memory device depicted in FIGS. 4A-4Iand FIG. 5 include 3D memory device 100 depicted in FIG. 1. FIGS. 4A-4Iand FIG. 5 will be described together. It is understood that theoperations shown in method 500 are not exhaustive and that otheroperations can be performed as well before, after, or between any of theillustrated operations. Further, some of the operations may be performedsimultaneously, or in a different order than shown in FIG. 5.

Referring to FIG. 5, method 500 starts at operation 502, in which afirst dielectric layer is formed on a substrate, and a first photoresistlayer is formed on the first dielectric layer. The substrate can be asilicon substrate. In some embodiments, prior to forming the firstdielectric layer, the substrate is doped by ion implantation and/orthermal diffusion to form doping regions (e.g., wells) and is oxidizedto form a silicon oxide film (e.g., ISSG silicon oxide). In someembodiments, isolation regions (e.g., shallow trench isolations (STIs))are also formed in the substrate by wet/dry etch and thin filmdeposition. Forming the first dielectric layer can include depositing asilicon oxide film on the substrate.

As illustrated in FIG. 4A, a dielectric layer 404 is formed on a siliconsubstrate 402. Dielectric layer 404 can include silicon oxide, such astetraethyl orthosilicate (TEOS) silicon oxide, or any other dielectricmaterials including, but not limited to, silicon nitride, siliconoxynitride, or any combination thereof. Dielectric layer 404 can beformed by one or more thin film deposition processes including, but notlimited to, chemical vapor deposition (CVD), physical vapor deposition(PVD), atomic layer deposition (ALD), spin coating, or any combinationthereof. A photoresist layer 406 is formed on dielectric layer 404 byspin coating. Photoresist layer 406 can be any suitable type of positiveor negative photoresist. In some embodiments, an ISSG silicon oxide filmis formed between dielectric layer 404 and silicon substrate 402, and abottom anti-reflection coating (BARC) film is formed between dielectriclayer 404 and photoresist layer 406.

Method 500 proceeds to operation 504, as illustrated in FIG. 5, in whicha recess is patterned through the first dielectric layer to thesubstrate by a plurality cycles of trimming the first photoresist layerand etching the first dielectric layer. In some embodiments, patterningthe recess includes patterning the first photoresist layer to expose aportion of the first dielectric layer, and etching the exposed portionof the first dielectric layer using the patterned first photoresistlayer as an etch mask. In each trim-etch cycle, the first photoresistlayer is trimmed to enlarge the exposed portion of the first dielectriclayer, and the enlarged exposed portion of the first dielectric layer isetched using the trimmed first photoresist layer as another etch mask toform a step structure at an edge of the recess, according to someembodiments. The trim-etch cycle can be repeated until the etchingreaches the substrate and results in a plurality of step structures atthe edge of the recess. In some embodiments, the amount of the trimmedfirst photoresist layer is nominally the same in each trim-etch cycle,and the width of each step structure is nominally the same as well.

As illustrated in FIG. 4B, photoresist layer 406 is patterned to exposeportions of dielectric layer 404. Photoresist layer 406 can be patternedby photolithography and development. Patterned photoresist layer 406 isused as an etch mask to etch the exposed portions of dielectric layer404 by wet etch and/or dry etch. Any suitable etchants (e.g., of wetetch and/or dry etch) can be used to remove a certain thickness ofdielectric layer 404 (and the entire thickness of BARC film if any) inthe exposed portions. The etched thickness can be controlled by etchrate and/or etch time. Patterned photoresist layer 406 is then trimmed(e.g., etched incrementally and inwardly, often from all directions) toenlarge the exposed portions of dielectric layer 404 (as indicated bythe lateral arrows). The amount of photoresist layer 406 trimmed can becontrolled by trim rate and/or trim time and can be directly relevant(e.g., determinant) to the dimensions of the resulting step structures408. The trim of photoresist layer 406 can be performed using anysuitable etch process, e.g., an isotropic dry etch or a wet etch. Theenlarged exposed portions of dielectric layer 404 are etched again usingtrimmed photoresist layer 406 as an etch mask to form one step structure408. Any suitable etchants (e.g., of wet etch and/or dry etch) can beused to remove a certain thickness of dielectric layer 404 towardsilicon substrate 402 (as indicated by the vertical arrows), which canbe controlled by etch rate and/or etch time. The trim process ofphotoresist 406 followed by the etch process of dielectric layer 404 isreferred to herein as a trim-etch cycle of dielectric layer 404.

As illustrated in FIG. 4C, the trim-etch cycle of dielectric layer 404is repeated until the etching reaches substrate 402. Consequently,recesses 410 are formed through dielectric layer 404 to substrate 402with a plurality of step structures 408 at the edges of recesses 410.Due to the repeated trim-etch cycles of dielectric layer 404, recess 410can have tilted side edges and a top aperture larger than the bottomaperture. That is, the aperture of recess 410 incrementally decreases asit goes toward silicon substrate 402. The number of step structures 408can be determined by the number of trim-etch cycles of dielectric layer404. The dimensions of each step structure 408 can be determined by theamount of trimmed photoresist layer 406 in each cycle (e.g., determiningthe width in the lateral direction) and by the thickness of etcheddielectric layer 404 in each cycle (e.g., determining the depth/heightin the vertical direction). In some embodiments, the amount of trimmedphotoresist layer 406 in each cycle is nominally the same, so that thewidth of each step structure 408 is nominally the same. In someembodiments, the thickness of etched dielectric layer 404 in each cycleis nominally the same, so that the depth/height of each step structure408 is nominally the same.

As illustrated in FIG. 4C, after recess 410 is patterned, remainingphotoresist layer 406 is removed, for example, by polymer ashing,photoresist stripping, and/or wet clean, to clean the outer surfaces(e.g., the top surface and the side edges of recess 410) of dielectriclayer 404. A silicon oxide film 412 is formed to cover silicon substrate402 exposed at the bottom of recess 410. In some embodiments, siliconoxide film 412 is formed by ISSG oxidation of silicon substrate 402,high density plasma (HDP) oxidation deposition, and/or fluorine siliconglass (FSG) oxidation deposition. In some embodiments, silicon oxidefilm 412 covers not only the bottom of recess 410, but also the outersurfaces (e.g., the top surface and the side edges of recess 410) ofdielectric layer 404.

Method 500 proceeds to operation 506, as illustrated in FIG. 5, in whicha plurality of dielectric/sacrificial layer pairs are formed on the topsurface of the first dielectric layer and filling in the recess. In someembodiments, forming the dielectric/sacrificial layer pairs includesalternatingly depositing dielectric layers and sacrificial layers. Thethickness of each dielectric/sacrificial layer pair is nominally thesame as the thickness of each step structure at the edge of the recess.Forming the dielectric/sacrificial layer pairs can also includeplanarizing the deposited dielectric layers and sacrificial layers. Insome embodiments, after the planarization, the number of thedielectric/sacrificial layer pairs on the top surface of the firstdielectric layer is the same as the number of the dielectric/sacrificiallayer pairs in the recess.

As illustrated in FIG. 4D, a plurality of dielectric/sacrificial layerpairs 414 are formed on the top surface of dielectric layer 404 (alsoreferred to herein as “upper dielectric/sacrificial layer pairs” 422)and filling in recesses 410 (also referred to herein as “lowerdielectric/sacrificial layer pairs 420”). In some embodiments,sacrificial layers 416 and dielectric layers 418 are alternatinglydeposited by one or more thin film deposition processes including, butnot limited to, PVD, CVD, ALD, or any combination thereof. In someembodiments, sacrificial layers 416 include silicon nitride, anddielectric layers 418 include silicon oxide. The deposition rate and/ordeposition time can be controlled such that the thickness of eachdielectric/sacrificial layer pair 414 (including the total thickness ofsacrificial layer 416 and dielectric layer 418) is nominally the same asthe depth/height of each step structure 408 at the edges of recess 410.Consequently, lower dielectric/sacrificial layer pairs 420 can include aplurality of step structures 408 at the edges of lowerdielectric/sacrificial layer pairs 420.

In some embodiments, the deposition of dielectric/sacrificial layerpairs 414 includes first filling in recess 410 until the top surface oflower dielectric/sacrificial layer pairs 420 flushes with the topsurface of dielectric layer 404. The deposition then can continue toform upper dielectric/sacrificial layer pairs 422 on the top surfaces oflower dielectric/sacrificial layer pairs 420 and dielectric layer 404.

It is understood that the sequence of depositing sacrificial layers 416and dielectric layers 418 is not limited. For depositing lowerdielectric/sacrificial layer pairs 420 filling in recesses 410, thedeposition can start with sacrificial layer 416 or dielectric layer 418and end with sacrificial layer 416 or dielectric layer 418. Similarly,for depositing upper dielectric/sacrificial layer pairs 422 on the topsurface of dielectric layer 404, the deposition can start withsacrificial layer 416 or dielectric layer 418 and end with sacrificiallayer 416 or dielectric layer 418. In FIG. 4D, the number of upperdielectric/sacrificial layer pairs 422 is larger than the number oflower dielectric/sacrificial layer pairs 420 to leave rooms forsubsequent planarization.

As illustrated in FIG. 4E, upper dielectric/sacrificial layer pairs 422are planarized by a plurality of processes. For example, a hard mask anda photoresist layer can be deposited and patterned by photolithographyand wet/dry etch to fill in the gaps in upper dielectric/sacrificiallayer pairs 422, followed by CMP and/or wet/dry etch to remove excessupper dielectric/sacrificial layer pairs 422. In some embodiments, theplanarization process is performed to make the number of upperdielectric/sacrificial layer pairs 422 the same as the number of lowerdielectric/sacrificial layer pairs 420. It is understood that in someembodiments, the numbers of upper dielectric/sacrificial layer pairs 422and lower dielectric/sacrificial layer pairs 420 are different.

Method 500 proceeds to operation 508, as illustrated in FIG. 5, in whicha second photoresist layer is formed on the top surface of thedielectric/sacrificial layer pairs. As illustrated in FIG. 4E,photoresist layer 424 is formed on the top surface of upperdielectric/sacrificial layer pairs 422 by spin coating and patterned byphotolithography and development. Photoresist layer 424 can be anysuitable type of positive or negative photoresist. In some embodiments,photoresist layer 424 is patterned to be aligned with the top of lowerdielectric/sacrificial layer pairs 420. For example, the same reticlesas lower dielectric/sacrificial layer pairs 420 (and recesses 410) canbe used, but with opposite photoresist patterns. In some embodiments, aBARC film is deposited between photoresist layer 424 and upperdielectric/sacrificial layer pairs 422 and similarly patterned asphotoresist layer 424.

Method 500 proceeds to operation 510, as illustrated in FIG. 5, in whichthe dielectric/sacrificial layer pairs are patterned by a pluralitycycles of trimming the second photoresist layer and etching theplurality of dielectric/sacrificial layer pairs. In some embodiments,patterning the dielectric/sacrificial layer pairs includes patterningthe second photoresist layer to expose a portion of a firstdielectric/sacrificial layer pair (e.g., the top dielectric/sacrificiallayer pair), and etching the exposed portion of the firstdielectric/sacrificial layer pair using the patterned second photoresistlayer as an etch mask to expose a second dielectric/sacrificial layerpair (e.g., the one beneath the top dielectric/sacrificial layer pair).In each trim-etch cycle, the second photoresist layer is trimmed toexpose another portion of the first dielectric/sacrificial layer pair,and the exposed portions of the first and second dielectric/sacrificiallayer pairs are etched using the trimmed second photoresist layer asanother etch mask to form a step structure at an edge of thedielectric/sacrificial layer pairs, according to some embodiments. Thetrim-etch cycle can be repeated until the etching reaches the topsurface of the first dielectric layer and results in a plurality of stepstructures at the edge of the dielectric/sacrificial layer pairs. Insome embodiments, the amount of the trimmed second photoresist layer isnominally the same in each trim-etch cycle, and the width of each stepstructure is nominally the same as well.

As illustrated in FIG. 4E, photoresist layer 424 is patterned to exposeportions of the top one of upper dielectric/sacrificial layer pairs 422.Patterned photoresist layer 424 is used as an etch mask to etch theexposed portions of the top one of upper dielectric/sacrificial layerpairs 422 by wet etch and/or dry etch. Any suitable etchants (e.g., ofwet etch and/or dry etch) can be used to remove the entire thickness ofthe top one of dielectric/sacrificial layer pairs 414 in the exposedportions (including sacrificial layer 416 and dielectric layer 418therein). The etched thickness can be controlled by etch-stop atdifferent materials (e.g., silicon nitride and silicon oxide) used indielectric/sacrificial layer pair 414. The etching of the exposedportions of the top one of upper dielectric/sacrificial layer pairs 422results in the exposure of portions of the one beneath the top one ofupper dielectric/sacrificial layer pairs 422.

As illustrated in FIG. 4F, patterned photoresist layer 424 is thentrimmed (e.g., etched incrementally and inwardly, often from alldirections) to expose another portion of the top one of upperdielectric/sacrificial layer pairs 422 (as indicated by the lateralarrows). The amount of photoresist layer 424 trimmed can be controlledby trim rate and/or trim time and can be directly relevant (e.g.,determinant) to the dimensions of the resulting step structures 426. Thetrim of photoresist layer 424 can be performed using any suitable etchprocess, e.g., an isotropic dry etch or a wet etch. Both the enlargedexposed portions of the top one of upper dielectric/sacrificial layerpairs 422 and the exposed portions of the one beneath the top one ofupper dielectric/sacrificial layer pairs 422 are etched using trimmedphotoresist layer 424 as an etch mask to form one step structure 426.Any suitable etchants (e.g., of wet etch and/or dry etch) can be used toremove the entire thickness of dielectric/sacrificial layer pair 414 inthe exposed portions (including sacrificial layer 416 and dielectriclayer 418 therein) toward silicon substrate 402 (as indicated by thevertical arrows). The trim process of photoresist layer 424 followed bythe etch process of dielectric/sacrificial layer pair 414 is referred toherein as a trim-etch cycle of dielectric/sacrificial layer pair 414.

As illustrated in FIG. 4F, the trim-etch cycle of dielectric/sacrificiallayer pair 414 is repeated until the etching reaches the top surface ofdielectric layer 404 (i.e., finishing the etching of the bottom one ofupper dielectric/sacrificial layer pairs 422). Consequently, upperdielectric/sacrificial layer pairs 422 are patterned with a plurality ofstep structures 426 at the edges of upper dielectric/sacrificial layerpairs 422. Due to the repeated trim-etch cycles ofdielectric/sacrificial layer pair 414, upper dielectric/sacrificiallayer pairs 422 can have tilted side edges and a topdielectric/sacrificial layer pair smaller than the bottom one. That is,the length of each one of upper dielectric/sacrificial layer pairs 422incrementally increases as it goes toward silicon substrate 402. Thenumber of step structures 426 can be determined by the number oftrim-etch cycles of dielectric/sacrificial layer pair 414. Thedimensions of each step structure 426 can be determined by the amount oftrimmed photoresist layer 424 in each cycle (e.g., determining the widthin the lateral direction) and by the thickness of dielectric/sacrificiallayer pair 414 (e.g., determining the depth/height in the verticaldirection). In some embodiments, the amount of trimmed photoresist layer424 in each cycle is nominally the same, so that the width of each stepstructure 426 is nominally the same. In some embodiments, the thicknessof dielectric/sacrificial layer pair 414 is nominally the same, so thatthe depth/height of each step structure 426 is nominally the same.

Method 500 proceeds to operation 512, as illustrated in FIG. 5, in whicha second dielectric layer is formed on the top surface of the firstdielectric layer and covering the patterned plurality ofdielectric/sacrificial layer pairs. Forming the second dielectric layercan include depositing a silicon oxide film and planarizing the siliconoxide film.

As illustrated in FIG. 4G, a dielectric layer 428 is formed on the topsurface of dielectric layer 404 and covering patterned upperdielectric/sacrificial layer pairs 422. Dielectric layer 428 can includesilicon oxide, such as TEOS silicon oxide, or any other dielectricmaterials including, but not limited to, silicon nitride, siliconoxynitride, or any combination thereof. Dielectric layer 428 can beformed by one or more thin film deposition processes including, but notlimited to, CVD, PVD, ALD, spin coating, or any combination thereof. Insome embodiments, an HDP and/or FSG silicon oxide film is depositedbetween dielectric layer 428 and dielectric layer 404 (and betweendielectric layer 428 and patterned upper dielectric/sacrificial layerpairs 422). As illustrated in FIG. 4H, dielectric layer 428 isplanarized by a plurality of processes. For example, a hard mask and aphotoresist layer can be deposited and patterned by photolithography andwet/dry etch to fill in the gaps in dielectric layer 428, followed byCMP and/or wet/dry etch to remove excess dielectric layer 428.

Method 500 proceeds to operation 514, as illustrated in FIG. 5, in whicha memory stack including a plurality of conductor/dielectric layer pairsis formed on the substrate by replacing, with a plurality of conductorlayers, the sacrificial layers in the patterned dielectric/sacrificiallayer pairs on the top surface of the first dielectric layer and thedielectric/sacrificial layer pairs in the recess. The process is alsoknown as “gate replacement process.” In some embodiments, the gatereplacement process includes etching a plurality of openings through thedielectric/sacrificial layer pairs, etching the sacrificial layers inthe dielectric/sacrificial layer pairs through the openings, anddepositing the conductor layers in the conductor/dielectric layer pairsthrough the openings.

As illustrated in FIG. 4I, openings 430 (e.g., gate line slits) areetched through patterned upper dielectric/sacrificial layer pairs 422and lower dielectric/sacrificial layer pairs 420. Openings 430 can beformed by wet etching and/or dry etching of dielectrics (e.g., siliconoxide and silicon nitride). Openings 430 are used as pathways for gatereplacement process that replaces sacrificial layers 416 in patternedupper dielectric/sacrificial layer pairs 422 and lowerdielectric/sacrificial layer pairs 420 with conductor layers 432 to forma plurality of conductor/dielectric layer pairs 434. The replacement ofsacrificial layers 416 with conductor layers 432 can be performed by wetetching sacrificial layers 416 (e.g., silicon nitride) selective todielectric layers 418 (e.g., silicon oxide) and filling the structurewith conductor layers 432 (e.g., W). Conductor layers 432 can bedeposited by PVD, CVD, ALD, any other suitable process, or anycombination thereof. Conductor layers 432 can include conductivematerials including, but not limited to, W, Co, Cu, Al, polysilicon,silicides, or any combination thereof.

As a result, after the gate replacement process, patterned upperdielectric/sacrificial layer pairs 422 in FIG. 4H become an upper memorystack 436 (e.g., part of memory stack 104 in upper deck 128 in FIG. 1),and lower dielectric/sacrificial layer pairs 420 in FIG. 4H become alower memory stack 438 (e.g., part of memory stack 104 in lower deck 126in FIG. 1). Upper memory stack 436 and lower memory stack 438 togetherbecome a memory stack 444 (e.g., memory stack 104 in FIG. 1) having asubstantially hexagon shape in the side view. Step structures 426 at theedges of patterned upper dielectric/sacrificial layer pairs 422 in FIG.4H become staircase structures 440 of upper memory stack 436 (e.g.,second and fourth staircase structures 124B and 124D in FIG. 1), andstep structures 408 at the edges of lower dielectric/sacrificial layerpairs 420 in FIG. 4H become staircase structures 442 of lower memorystack 438 (e.g., first and third staircase structures 124A and 124C inFIG. 1). It is understood that details of forming other components inmemory stack 444 (e.g., NAND memory strings) and local interconnects(e.g., word line via contacts) can be readily appreciated and thus, arenot described herein.

The foregoing description of the specific embodiments will so reveal thegeneral nature of the present disclosure that others can, by applyingknowledge within the skill of the art, readily modify and/or adapt forvarious applications such specific embodiments, without undueexperimentation, without departing from the general concept of thepresent disclosure. Therefore, such adaptations and modifications areintended to be within the meaning and range of equivalents of thedisclosed embodiments, based on the teaching and guidance presentedherein. It is to be understood that the phraseology or terminologyherein is for the purpose of description and not of limitation, suchthat the terminology or phraseology of the present specification is tobe interpreted by the skilled artisan in light of the teachings andguidance.

Embodiments of the present disclosure have been described above with theaid of functional building blocks illustrating the implementation ofspecified functions and relationships thereof. The boundaries of thesefunctional building blocks have been arbitrarily defined herein for theconvenience of the description. Alternate boundaries can be defined solong as the specified functions and relationships thereof areappropriately performed.

The Summary and Abstract sections may set forth one or more but not allexemplary embodiments of the present disclosure as contemplated by theinventor(s), and thus, are not intended to limit the present disclosureand the appended claims in any way.

The breadth and scope of the present disclosure should not be limited byany of the above-described exemplary embodiments, but should be definedonly in accordance with the following claims and their equivalents.

What is claimed is:
 1. A three-dimensional (3D) memory device,comprising: a substrate; a memory stack disposed on the substrate andcomprising a plurality of conductor/dielectric pairs, wherein theconductor/dielectric pairs comprise a plurality of conductor layers anddielectric layers stacked alternatingly; and an array of memory stringseach extending vertically through an inner region of the memory stack,wherein an outer region of the memory stack comprises a first staircasestructure disposed on the substrate and a second staircase structuredisposed above the first staircase structure; first edges of theplurality of conductor/dielectric layer pairs in the first staircasestructure along a vertical direction away from the substrate arestaggered laterally away from the array of memory strings; and secondedges of the plurality of conductor/dielectric layer pairs in the secondstaircase structure along the vertical direction away from the substrateare staggered laterally toward the array of memory strings.
 2. The 3Dmemory device of claim 1, wherein: the outer region of the memory stackfurther comprises a third staircase structure disposed on the substrateand a fourth staircase structure disposed above the third staircasestructure; third edges of the plurality of conductor/dielectric layerpairs in the third staircase structure along the vertical direction awayfrom the substrate are staggered laterally away from the array of memorystrings; and fourth edges of the plurality of conductor/dielectric layerpairs in the fourth staircase structure along the vertical directionaway from the substrate are staggered laterally toward the array ofmemory strings.
 3. The 3D memory device of claim 1, wherein a length ofeach of the conductor/dielectric layer pairs decreases from a middleconductor/dielectric layer pair toward top and bottomconductor/dielectric layer pairs, respectively.
 4. The 3D memory deviceof claim 2, wherein a first number of the conductor/dielectric layerpairs in each of the first and third staircase structures is the same,and a second number of the conductor/dielectric layer pairs in each ofthe second and fourth staircase structures is the same.
 5. The 3D memorydevice of claim 4, wherein the first number is the same as the secondnumber.
 6. The 3D memory device of claim 1, further comprising: a firstinterconnect layer disposed below the memory stack; and a plurality offirst via contacts each in contact with a conductor layer in one of theconductor/dielectric layer pairs in the first staircase structure, thefirst via contacts each electrically connected to the first interconnectlayer.
 7. The 3D memory device of claim 6, wherein: the firstinterconnect layer and the memory stack are disposed at opposite sidesof the substrate; and the 3D memory device further comprises a pluralityof second via contacts each extending through the substrate andelectrically connected to the first interconnect layer and one of thefirst via contacts.
 8. The 3D memory device of claim 1, furthercomprising: a second interconnect layer disposed above the memory stack;and a plurality of third via contacts each in contact with a conductorlayer in one of the conductor/dielectric layer pairs in the secondstaircase structure, the third via contacts each electrically connectedto the second interconnect layer.
 9. The 3D memory device of claim 1,wherein: the first edges of each adjacent conductor/dielectric layerpairs in the first staircase structure are staggered laterally away fromthe array of memory strings, and the second edges of each adjacentconductor/dielectric layer pairs in the second staircase structure arestaggered laterally toward the array of memory strings.
 10. The 3Dmemory device of claim 9, wherein an offset of the first edges of eachadjacent conductor/dielectric layer pairs in the first staircasestructure is the same as an offset of the second edges of each adjacentconductor/dielectric layer pairs in the second staircase structure. 11.The 3D memory device of claim 1, wherein the memory stack has asubstantial hexagon shape in a side view.
 12. A three-dimensional (3D)memory device, comprising: a substrate; a memory stack disposed on thesubstrate and comprising a plurality of conductor/dielectric pairs,wherein the conductor/dielectric pairs comprise a plurality of conductorlayers and dielectric layers stacked alternatingly, and a length of eachconductor/dielectric layer pair decreases from a middle of the memorystack to a bottom of the memory stack, wherein the bottom of the memorystack is adjacent to the substrate; and an array of memory strings eachextending vertically through an inner region of the memory stack,wherein an outer region of the memory stack comprises a first staircasestructure disposed on the substrate and a second staircase structuredisposed on the substrate; first edges of the plurality ofconductor/dielectric layer pairs in the first staircase structure alonga vertical direction away from the substrate are staggered laterallyaway from the array of memory strings; and second edges of the pluralityof conductor/dielectric layer pairs in the second staircase structurealong the vertical direction away from the substrate are staggeredlaterally away from the array of memory strings.
 13. A three-dimensional(3D) memory device, comprising: a substrate; a memory stack disposedabove the substrate and comprising a plurality of conductor/dielectricpairs, wherein the conductor/dielectric pairs comprise a plurality ofconductor layers and dielectric layers stacked alternatingly, andwherein a length of each of the conductor/dielectric layer pairsdecreases from a middle conductor/dielectric layer pair toward a topconductor/dielectric layer pair and a bottom conductor/dielectric layerpair, respectively; and an array of memory strings each extendingvertically through the memory stack.
 14. The 3D memory device of claim13, further comprising: a first interconnect layer disposed above thememory stack; and a plurality of first via contacts in contact with theconductor layers in some of the conductor/dielectric layer pairs,respectively, the first via contacts electrically connected to the firstinterconnect layer.
 15. The 3D memory device of claim 13, furthercomprising: a second interconnect layer disposed below the memory stack;and a plurality of second via contacts in contact with the conductorlayers in some of the conductor/dielectric layer pairs, respectively,the second via contacts electrically connected to the secondinterconnect layer.
 16. The 3D memory device of claim 15, wherein: thesecond interconnect layer and the memory stack are disposed at oppositesides of the substrate; and the 3D memory device further comprises aplurality of third via contacts extending through the substrate andelectrically connected to the second interconnect layer and the secondvia contacts.
 17. The 3D memory device of claim 13, wherein: first edgesof one side of each adjacent conductor/dielectric layer pairs arestaggered laterally; and second edges on another side of each adjacentconductor/dielectric layer pairs are staggered laterally.
 18. The 3Dmemory device of claim 17, wherein: a first offset of the first edges ofeach adjacent conductor/dielectric layer pairs is the same; and a secondoffset of the second edges of each adjacent conductor/dielectric layerpairs is the same.
 19. The 3D memory device of claim 18, wherein thefirst offset if the same as the second offset.
 20. The 3D memory deviceof claim 13, wherein the memory stack has a substantially substantialhexagon shape in a side view.